International Coverage
June 21, 2010
Japan
Tech-On!
Toshiba, et al Develop 3D FPGA
By Motoyuki Ooishi, Nikkei Electronics
Toshiba Corp realized a so-called "3D FPGA" by three-dimensionally stacking SRAMs based on amorphous silicon (Si) TFT technology on a CMOS logic circuit in collaboration with Covalent Materials Corp., Tier Logic, Inc. and TEI Technology.
The 3D FPGA was announced at the 2010 Symposium on VLSI Technology, an international conference on semiconductor manufacturing technologies that took place from June 15 to 17, 2010, in Honolulu, Hawaii (thesis number: 21.1).
Original Japanese version
June 13, 2010
Sri Lanka
The Sunday Times
Sri Lankans assist in building a unique global chip
In the Integrated Circuits (IC) industry, USA's Silicon Valley and a Colombo-based start up company Tier Logic Inc. have introduced a novel 3-dimensional IC which is used in the automotive, communications and IT, consumer, data processing and industrial market segments. This is the first monolithic semiconductor IC in the world to use thin-film transistors.
Holland
Bits&Chips
Logic is more flexible
By Pieter Edelman
The semiconductor industry is always facing a trade-offs between flexibility and energy efficiency. Manufacturing has high startup costs, the chip must first be designed and expensive masks must be produced before production can begin. The industry has therefore created a wide range of intermediate forms between generic and application-specific forms.
May 28, 2010
Italy
EO News
3D FPGAs: solving the design "dilemma"
Which technology to choose for implementing electronic systems—devices that use an FPGA (field-programmable gate array) chip, or an ASIC (application-specific integrated circuit)—has traditionally been a dilemma for engineers in the embedded field.
May 18, 2010
Italy
Il Sole 24 Ore
3D FPGAs
The chip is jumping to the third dimension, thanks to the work of startups like Tier Logic. Tier Logic in particular stacks transistors and other components in a multi-layer structure. One layer contains the basic functions of the chip. The upper layer holds the memory cell with programming instructions. The cells are made with TFTs (thin film transistors).
May 16, 2010
Germany
Markt&Technik
Third Dimension—the First
Almost simultaneously, two new PLD startups announced the third dimension. Tier Logic places the configuration circuits not on the plane with the actual logic, but above the logic at the ninth metal layer.
April 10, 2010
Germany
Elektronik Praxis
Risk-free and cost-efficient conversion of FPGAs to ASICs
By Holger Heller
With its 3-D FPGA technology, Tier Logic offers low-cost FPGAs and risk-free ASICs with exact timing.
March 17, 2010
Japan
USFL.COM
Two startups use 3D structure for performance innovation and cost reduction
Two FPGA start-ups based in Silicon Valley have developed new 3D techniques.
March 16, 2010
Europe
EDN Europe
3D-FPGA technology yields low-cost FPGAs and risk-free timing-exact ASICs
Start-up Tier Logic offers free NRE to first-round customers
...Tier Logic increases the effective logic density of its programmable array by taking the SRAM memory cells that configure the logic out of the main array and placing them in a layer of amorphous silicon that its process deposits on top of the metal layers that interconnect the chip’s active devices.
March 12, 2010
Denmark
Elektronik & Data
Another new player launches 3D FPGA technology
…Although Tier Logic’s 3D structure is different from other FPGAs, users will be very familiar with the architecture and tool flow when they design with the Mobius tools from Tier Logic because they have the same features as existing FPGA providers and the design flow is exactly the same.
March 11, 2010
Finland
Prosessori
Tier Logic delivers cheaper, faster and denser chips:
3D programmable logic
By Veijo Ojanperä
The FPGA market is in a real turmoil. It has long been dominated by Xilinx and Altera. A new kind of 3D architecture is now is becoming available. The newest entrant is Tier Logic.
Original Finnish version
Germany
FPGA News.de
Tier Logic announces TierFPGA family
By Guy Eschemann
Soon it will be spring, and the FPGA startups are shooting from the ground like crocuses.
Original German version
Sweden
Elektroniktidningen
Both FPGA and ASIC
By Per Henricsson
At first glance, U.S. start-up company Tier Logic's offering appears similar to Hardcopy from FPGA giant Altera. But Tier Logic's approach is radically different, which makes room for more logic blocks per unit area. The company can also provide identical features in an ASIC and an FPGA, all at a lower price.
Original Swedish version
January 8, 2010
Japan
Tech Village
Creative, disruptive technology from emerging companies
By Yamamoto Osamu
An overview of emerging venture-backed FPGA companies.
September 9, 2009
Taiwan
EE Times Taiwan
FPGA start-up strengths and risks analysis
By Mai Dailun
As a high-growth, high-profit market, programmable logic has attracted venture capitalists and attention. Since 1983, more than 50 new companies have been involved in the market.
Tier Logic In the News
May 24 2010
New Electronics
The future’s bright … the future’s programmable logic
By Graham Pitcher
In the 1990s, programmable logic was being touted as the technology of the future. The ability to do with it almost what you wanted was seen as the route to true systems on chips and programmable logic was set to grab a serious chunk of the ASIC business.
May 12, 2010
TechBites
Convert your existing Altera/Xilinx FPGAs to Tier Logic ASICs for $0!
by Clive Maxfield
Good Grief. The folks at Tier Logic have come up with a rather bold move, which is to take your existing FPGA designs from Altera or Xilinx and convert them into equivalent ASICs for FREE (by which I mean $0 NRE and free conversion).
MeMyselfMax on YouTube
FPGAs and ASICs from Tier Logic
by Clive Maxfield
…If you have any concerns about working with a startup, your designs can be placed in escrow with Toshiba, which means that should anything happen to Tier Logic, Toshiba will continue to manufacture the devices and supply them to you directly.
DATAWEEK
Programmable logic goes 3D
A privately held, fabless semiconductor startup company called Tier Logic has introduced new 3D-based technology for FPGAs and ASICs, known respectively as TierFPGA and TierASIC devices.
April 13, 2010
FPGA Journal
Taming Thin Film:
Tier Logic's Approach to 3D FPGAs
by Kevin Morris
Apparently, having an old 2D FPGA on your development board will soon be as lame as having one of those old-school 2D flatscreen TVs on your wall. Sure, 2D FPGAs are good, but the buzz is all about 3D these days. If it hasn't got a Z axis, we easily-distracted trade press editors may not see it sticking up past all the other bright, shiny objects.
New Electronics
How programmable logic is adding another dimension to its abilities.
By Graham Pitcher
…But two new entrants into the programmable logic market believe they can change things and both companies – Tabula and Tier Logic – believe they can do this using a third dimension. The difference between the two is their definition of that third dimension: Tabula defines it as time, while Tier Logic defines it as physical depth.
Semiconductor Times/Pinestream Communications
Tier Logic 3D FPGA products—company profile
…The company has been very capital efficient and has developed silicon and tools, developed a process technology, and secured initial orders while still on a first round of financing – all achieved for less than $20 million. Tier Logic has 25 employees in Santa Clara, CA and 25 in Colombo, Sri Lanka.
March 25, 2009
The Linley Group—Linley Chips In
Innovation Disrupts FPGA Duopoly
By Jag Bolaria
…Technology from two new companies, Tabula and Tier Logic, poses a greater threat to the FPGA duopoly. These startups have fundamentally changed the FPGA silicon architecture to offer midrange and high-end FPGAs at low-end prices. If Xilinx and Altera attempt to follow suit using their current architectures, they would ruin their margin structure.
Tier Stacks FPGA Memory to Cut Cost
By Jag Bolaria
Perhaps spurred by Tabula's announcement, Tier Logic recently came out of stealth mode to discuss its technology for reducing the cost of FPGAs. Although both companies use the term 3D to describe their approaches, Tabula uses time as its third dimension, whereas Tier works in the more traditional third dimension of verticality.
March 23, 2010
Electronics Weekly
3D FPGAs present major cost and design efficiencies (see pages 16-17)
View the article in PDF form here
By David Manners
Tier Logic has come out of seven years in stealth mode to launch its 3D FPGAs. The company is open for business now, and is offering free non-recurring engineering (NRE) to early adopters.
March 16, 2010
The Wall Street Journal
Start-Ups Add Third Dimension to Chips
If you are not a Wall Street Journal subscriber, view the article here
By Don Clark
A perennial race to squeeze more features on flat pieces of silicon is taking a step into the third dimension.
Two Silicon Valley start-ups are breaking from conventional designs—which lay out components on chips in two-dimensional patterns—to develop products that are configured by customers after they are manufactured. Such programmable chips are a popular choice for some devices, such as computer-networking gear, but are considered too expensive for many high-volume applications.
Electronics Weekly
3D FPGAs could kickstart the market (See page 8)
View the article in PDF form here
By David Manners
It is good to see innovation taking place in programmables. This is a product area which has remained stuck in a $3bn market niche for a decade.
Silicon Valley start-up Tier Logic has come up with a monolithic FPGA/Asic chip which cuts the cost of programmables and may kick-start growth in the sector.
March 12, 2010
Can Tabula and Tier Logic be successful?
By Olivier Coudert
The past two weeks were pretty interesting if you follow FPGAs. Yes, Xilinx and Altera kept upping their target to Wall St., but that is not where the excitement came from. It came from the recent announcements of two startups, both created in 2003 and heavily funded. Tabula released its long-awaited device, which goes by the sexy name of “Spacetime”. And Tier Logic left its stealth mode this week to announce its own device, “TierFPGA”.
March 11, 2010
VentureWire
Tier Logic, Tabula Unveil Programmable Chip Products
If you are not a VentureWire subscriber, view the article here
By Scott Denne
As the cost of building application-specific integrated circuits continues to rise, two start-ups have announced new programmable products that could go a long way to mitigating the price increase. The latest is Tier Logic Inc., which expects to be producing large volumes of its TierASIC chips before the second half of the year, according to Paul Hollingworth, its vice president of marketing and sales.
March 10, 2010
TechBites
Tier Logic's 3D-FPGA technology = low-cost FPGAs and no-risk ASICs
By Clive Maxwell
…Come on... you have to admit that this is very, VERY clever!
EDN—Practical Chip Design
Tier Logic lifts the veil: another take on the 3D FPGA
By Ron Wilson
Tier Logic's big idea is elegant and audacious: increase the density of FPGAs by moving all the configuration memory—not the data memory or the look-up-table (LUT) memory, but the RAM cells that control the interconnect muxes—out of the silicon.
EE Times
FPGA startup: Process tech eases ASIC migration
Tier Logic approach uses 3-D stacked layers to create 'first monolithic 3-D FPGA'
By Dylan McGrath
The key is that Tier Logic's 3-D TierFPGA features one level, or tier, of thin-film transistor (TFT)-based SRAM, creating a more efficient device than a traditional 2-D FPGA, a large percentage of which is configuration SRAM, according to Paul Hollingworth, a 23-year-veteran of the chip industry who serves as Tier Logic's vice president of sales and marketing.
EDN—FPGA Gurus
Tier Logic's Threefold Path
By Loring Wirbel
Tier Logic’s vice president of sales and marketing Paul Hollingworth clued me in on the company’s threefold path to profitability, which frankly makes a lot more tactical sense than what I’ve heard from other startups of late.
Electronics Weekly
Tier Logic Launches 3D FPGAs
By David Manners
Today, Tier Logic breaks out of its seven years in Stealth Mode to launch its 3D FPGAs. The company is open for business now, and is offering free NREs to early adopters.
Electronics Weekly—Mannerisms
Tier Logic Reduces Cost Of FPGA, ASIC, & FPGA-ASIC Conversion
By David Manners
It's good to see innovation taking place in programmables. This is a product area which has remained stuck in a $3 billion market niche for a decade. Silicon Valley start-up Tier Logic today announces a route to bringing down programmables' costs which may kick-start growth in the sector.
New Electronics
Tier Logic comes out of stealth, targets design and production needs
By Graham Pitcher
Tier Logic separates user circuits and configuration circuits into stacked layers. By removing the configuration overhead from the silicon base layers, Tier Logic says it can produce smaller, denser, faster, lower power and more reliable fpgas.
SOC Central
Tier Logic Announces 3D-Based Technology for FPGAs and ASICs
...Tier Logic founder and CTO Raminda Madurawe commented, "The innovation of Tier Logic's monolithic 3D-FPGA significantly enhances the value of programmable solutions. By moving programmable overhead into the third dimension, we improve cost, power, performance, and security – all of the drawbacks associated with traditional FPGAs – without losing programmability. We can remove this overhead completely from the device without altering implemented designs to offer users timing-exact, very-low-cost ASICs--something traditional FPGAs simply can't offer."
Design & Reuse
Tier Logic announces innovative 3D-FPGA technology: low-cost FPGAs & no-risk, timing-exact ASICs
Early Access Program offers free NRE
Tier Logic, Inc., a privately held fabless semiconductor company, today introduced its new 3D-based technology for FPGAs and ASICs, known respectively as its TierFPGA™ and TierASIC™ devices.
March 8, 2010
Electronics Weekly—Mannerisms
A New Contender For 3D FPGA Emerges This Week
By David Manners
This week sees another contender enter the ring for the emerging 3D FPGA market tussle. Tier Logic will reveal on Wednesday what it has been working on in stealth mode since 2003. Like others in the 3D FPGA market, Tier Logic's focus is to site the configuration logic in a way that doesn't diminish the density of the logic array or affect the performance of the chip.
February 22, 2010
Electronics Weekly
Tier Logic Resists Far Eastern Delights
By David Manners
FPGA start-up Tier Logic, currently beavering away in Stealth Mode in Santa Clara, has reassured its IC designers that their jobs won't be relocated to exotic, Far Eastern climes.
February 11, 2010
VentureWire
Former Cswitch CEO Doug Laird Joins Stealthy Tier Logic
If you are not a VentureWire subscriber, view the article here
By Scott Denne
Doug Laird, former chief executive of communications semiconductor maker Cswitch Inc., has taken the same post at programmable logic company Tier Logic Inc. Santa Clara, Calif.-based Tier Logic is a stealthy programmable logic company that is using three-dimensional design to combine the best features of programmable and static logic chips.
2009 Tier Logic News Coverage
October 5, 2009
Programmable Logic DesignLine
FPGAs well represented on Silicon 60
By Dylan McGrath
Three of the six active FPGA startups we've been tracking at Programmable Logic DesignLine made the cut and were included in version 9.0 of EE Times' Silicon 60 emerging startups.
July 28, 2009
EE Times
Sizing up the contenders
By Dylan McGrath
Even less is known about Tier Logic, another Santa Clara startup in stealth mode.
July 27, 2009
EE Times
FPGA startups stare down giants and ghosts
By Dylan McGrath
Even with the demise of Cswitch, today there are at least five active programmable logic startups whose outlooks are considered promising--more than at any time in recent memory.
July 16, 2009
EDN—FPGA Gurus
Loose threads and blank slates
By Loring Wirbel
I want to stress the positive case that there are still good ideas out there, most notably at the two companies that said the least to EE Times, Tabula Inc. and Tier Logic Inc.
May 15, 2009
EDN—FPGA Gurus
Blue state blues
By Loring Wirbel
…In the latter realm, a startup must compete with the both the expertise of the Xilinx-Altera-Actel-Lattice foursome in shrinking complex architectures, and with the ability of the market leaders to gain easy access to sub-90-nm foundry. This is why designers like Tier Logic have focused on architecture rather than speed or density.
April 20, 2009
EDN—FPGA Gurus
An FPGA startup in 2009?
By Loring Wirbel
Despite the graveyard of hopeful FPGA startups that lost funding since the start of the millennium, this column predicted at the end of 2008 that, no matter how bad conditions were, the Xilinx-Altera-Actel-Lattice Big Four might face some new competition emerging in 2009.
