Tier Logic Executive Team
Doug Laird
President & CEOMSCS, Santa Clara University
BSEE, Rochester Institute of Technology
Doug Laird has over 31 years of semiconductor industry experience, including serving as Cswitch's CEO and Transmeta's executive VP of product development. Earlier in his career, Laird held leadership positions at LSI Logic and Sun Microsystems.
Raminda Madurawe
Founder and CTOMS, Chemical Engineering, MIT
MSEE , Stanford
BS, Indian Institute of Technology (Madras)
Raminda Madurawe invented the 3D FPGA concept and founded Tier Logic in March 2002. He has over 23 years of experience in FPGAs and has been awarded 100 patents; 50 of those at Tier Logic. Before founding Tier Logic, Madurawe spent the bulk of his career at Altera Corp. and National Semiconductor in a variety of areas including product, test, and process engineering.
Dr. Peter Suaris
VP, Tools & Software; Co-founderPhD, Computer Science, Duke
MS, Operations Research, University of Kentucky
BSEE, University of Moratuwa
Peter Suaris has over 20 years of experience in ASIC and FPGA synthesis and tools with Mentor Graphics and Cadence. While at Mentor Graphics, Suaris pioneered physical synthesis. He has three pending patent applications with Tier Logic.
Tim Garverick
VP, Hardware EngineeringBSEE, MIT
Tim Garverick has over 27 years of experience in IC design and production, and has been awarded 11 patents. Before coming to Tier Logic, Garverick founded Adaptive Silicon. He was also VP, hardware engineering and operations at Stretch, Inc. and engineering director at National Semiconductor.
Paul Hollingworth
VP, Sales & MarketingMSEE and BSEE, University of Durham, UK
Paul Hollingworth brings over 23 years of product and technical marketing experience in the semiconductor industry. He comes to Tier Logic after 13 years at Altera, where, for the last five years, he ran the HardCopy ASIC business. Before Altera, he worked for 11 years in the ASIC industry, at LSI Logic and mixed-signal pioneer and top-10 foundry X-Fab.
Dr. Shuji (Shu) Ikeda
Consultant & Director of TechnologyPhD, Electrical Engineering, Tokyo Institute of Technology
MSEE, Princeton
BS, Physics, Tokyo Institute of Technology
Shuji Ikeda has over 30 years in the semiconductor industry. Honors include the 2004 IEEE Fellowship and chairing 2002 IEDM. He has been awarded over 70 U.S. patents and over 200 Japanese patents. Shu's career includes leadership positions at Hitachi; Trecenti Technologies; ATDF, the Advanced Technology Development Fab in Texas; and tei Technology. He is currently an Administrative Committee-elected member of IEEE.
